Infrastruktur
- Beziehungen:
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- Artificial Intelligence and Signal Processing
- Quick Generation of SSD Performance Models Using Machine Learning
- FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic
- Speedup analysis in simulation-emulation co-operation
- Using Input-to-Output Masking for System-level Vulnerability estimation in high-performance processors
- Soft Error Mitigation for SRAM-Based FPGAs
- A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design
- A hybrid fault injection approach based on simulation and emulation co-operation
- Estimating Error Propagation Probabilities with Bounded Variances
- System-Level Vulnerability Estimation for Data Caches
- An Accurate SER Estimation Method Based on Propagation Probability
- Balancing Performance and Reliability in the Memory Hierarchy
- An Analytical Approach for Soft Error Rate Estimation in Digital Circuits
- Fault injection into SRAM-based FPGAs for the analysis of SEU effects
- Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs
- Case Study: Soft Error Rate Analysis in Storage Systems
- Soft Error Derating Computation in Sequential Circuits
- STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation
- A Machine Learning Approach for Power Gating the FPGA Routing Network
- Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing
- ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms.
- Improving checkpointing intervals by considering individual job failure probabilities.
- DiskAccel
- Soft error modeling and remediation techniques in ASIC designs
- Obtaining FPGA soft error rate in high performance information systems
- Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems
- Analytical techniques for soft error rate Modeling and mitigation of FPGA-based designs
- Fast co-verification of HDL models
- Fast prototyping with co-operation of simulation and emulation
- A Modeling Framework for Reliability of Erasure Codes in SSD Arrays
- A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs
- Estimating and Mitigating Aging Effects in Routing Network of FPGAs
- Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era
- Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems
- Introduction: Special Section on Architecture of Future Many Core Systems
- A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices
- CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors
- Impact of stripe unit size on performance and endurance of SSD-based RAID arrays
- Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems
- A Power Gating Switch Box Architecture in Routing Network of SRAM-Based FPGAs in Dark Silicon Era
- An Efficient Reconfigurable Architecture by Characterizing Most Frequent Logic Functions
- 3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison
- Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems
- Computational Techniques for the Analysis of Small Signals in High-Statistics Neutrino Oscillation Experiments
- Implementation and Parallel Optimization of the Lees-Edwards Boundary Condition in ESPResSo++
- Reducing data cache susceptibility to soft errors
- Layout-Based Modeling and Mitigation of Multiple Event Transients
- PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era
- HAFTA: Highly Available Fault-Tolerant Architecture to Protect SRAM-Based Reconfigurable Devices Against Multiple Bit Upsets
- Efficient algorithms to accurately compute derating factors of digital circuits
- A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches
- An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors
- CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers
- FTSPM: A Fault-Tolerant ScratchPad Memory
- Performance and Availability Modeling of Hybrid Storage Systems
- Assessment of TCP parameters for mobile devices concerning performance and energy consumption
- Estimating Availability-oriented Throughput of Virtualized Networks
- Performability Model for Assessing NoSQL DBMS Consistency
- Stochastic modeling for performance and availability evaluation of hybrid storage systems
- A modeling approach for estimating performance and energy consumption of storage systems
- Energy Consumption Evaluation of LPWAN: A Stochastic Modeling Approach for IoT Systems
- Performance and Energy Consumption Evaluation of Hybrid Storage Systems
- Analytical models for performance and energy consumption evaluation of storage devices
- Simurgh
- Reconstruction of Low Energy Neutrino Events with GPUs at IceCube
- LBICA: A Load Balancer for I/O Cache Architectures
- An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories.
- FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for Add Intensive Applications
- An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems
- Ultrafast dynamics induced by the interaction of molecules with electromagnetic fields: Several quantum, semiclassical, and classical approaches
- Kinetic isotope effects and how to describe them
- Identification and Characterization of an Anti-Fibrotic Benzopyran Compound Isolated from Mangrove-Derived Streptomyces xiamenensis
- DelveFS - An Event-Driven Semantic File System for Object Stores
- ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization
- An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs
- Vibrational Spectroscopy and Proton Transfer Dynamics in Protonated Oxalate
- Spectroscopy and dynamics of double proton transfer in formic acid dimer
- Multicomponent kinetic analysis and theoretical studies on the phenolic intermediates in the oxidation of eugenol and isoeugenol catalyzed by laccase
- Vibrational Relaxation and Energy Migration of N-Methylacetamide in Water: The Role of Non bonded Interactions
- Pure Functions in C: A Small Keyword for Automatic Parallelization
- Challenges and Solutions for Tracing Storage Systems: A Case Study with Spectrum Scale
- Pure Functions in C: A Small Keyword for Automatic Parallelization
- Using On-Demand File Systems in HPC Environments
- An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture
- Operating system level data tiering using online workload characterization
- Reconfigurable caching
- ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms
- Tracing of Complex Production Systems: Obstacles and Solutions
- Analyzing File Create Performance in IBM Spectrum Scale
- ADA-FS - Advanced Data Placement via Ad hoc File Systems at Extreme Scales
- Multistate Reactive Molecular Dynamics Simulations of Proton Diffusion in Water Clusters and in the Bulk
- GekkoFS - A Temporary Distributed File System for HPC Applications
- GekkoFS - A Temporary Burst Buffer File System for HPC Applications
- Ad Hoc File Systems for High-Performance Computing
- Online Management of Hybrid DRAM-NVMM Memory for HPC
- Quantum Circuit Compiler for a Shuttling-Based Trapped-Ion Quantum Computer
- RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks
- Algorithmic Differentiation for Sensitivity Analysis in Cloud Microphysics
- Enabling Automatic OpenACC Program Parallelization Using Pure Functions
- Dependability Analysis of Data Storage Systems in Presence of Soft Errors
- Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems
- A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits
- On Endurance of Erasure Codes in SSD-based Storage Systems
- CLASS: Combined Logic and Architectural Soft Error Sensitivity Analysis
- Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays
- Computer Networks and Distributed Systems
- A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology
- TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches
- Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices
- On endurance and performance of erasure codes in SSD-based storage systems
- A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
- Stress-Aware Routing to Mitigate Aging Effects in SRAM-based FPGAs
- A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization
- Emerging Non-Volatile Memory Technologies for Future Low Power Reconfigurable Systems
- Evaluating Impact of Human Errors on the Availability of Data Storage Systems
- Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates
- A layout-based approach for multiple event transient analysis
- A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry
- Towards dark silicon era in FPGAs using complementary hard logic design
- An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories
Besitzt PublikationDie Publikationsliste für die Kategorie "Organisationseinheit" zeigt alle Publikationen, die der einzelnen Organisationseinheit direkt zugeordnet sind. Für eine Liste, die auch alle Publikationen von untergeordneten Organisationseinheiten inkludiert, nutzen Sie die Liste in der Facette "Organisationseinheit".
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